In modern microprocessor design, there is a trend toward increasing operating speeds, cache sizes, and, therefore, the size of cache directory address tags. There is an accompanying increase in the likelihood of errors in the information, such as address tags, stored in a cache directory. For example, a tag having more bits has increased occurrences of a alpha particle having flipped a bit. Thus, error detection is increasingly important. Error detection of this sort typically involves comparing redundant information for consistency.
One conventional way that microprocessor operating speed is increased is to employ dynamic logic circuitry. Such circuitry is particularly useful for control logic associated with cache directories because the speed of comparing address tags may be a limiting factor in the speed of reading and writing to a cache. However, dynamic circuitry is not well suited to logical inversions, which are required for comparing bits or bytes of information, for example to detect data errors.
Accordingly, what is needed is a method and system for fast and efficient detection of data errors. The need is particularly acute for such a method and system that is compatible with dynamic logic circuitry. The present invention addresses such a need.